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| DS1644/DS1644P Nonvolatile Timekeeping RAM www.maxim-ic.com FEATURES Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit and Lithium Energy Source Clock Registers are Accessed Identically to the Static RAM. These Registers are Resident in the Eight Top RAM Locations. Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power BCD-Coded Year, Month, Date, Day, Hours, Minutes, and Seconds with Leap Year Compensation Valid Up to 2100 Power-Fail Write Protection Allows for 10% VCC Power Supply Tolerance DS1644 Only (DIP Module) Upward Compatible with the DS1643 Timekeeping RAM to Achieve Higher RAM Density Standard JEDEC Bytewide 32k x 8 Static RAM Pinout DS1644P Only (PowerCap(R) Module Board) Surface Mountable Package for Direct Connection to PowerCap Containing Battery and crystal Replaceable Battery (PowerCap) Power-Fail Output Pin-for-Pin Compatible with Other Densities of DS164XP Timekeeping RAM Underwriters Laboratory (UL) Recognized PIN CONFIGURATIONS A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 28-Pin Encapsulated Package (720-mil Extended) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 NC NC A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 NC NC NC PFO VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND X1 GND VBAT X2 34-Pin PowerCap Module Board (Uses DS9034PCX PowerCap) PowerCap is a registered trademark of Dallas Semiconductor. ORDERING INFORMATION PART DS16440120+ DS16440-120 DS1644P120+ DS1644P-120 VOLTAGE RANGE (V) 5.0 5.0 5.0 5.0 TEMP RANGE PIN-PACKAGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 32 EDIP (0.740a) 32 EDIP (0.740a) 34 PowerCap* 34 PowerCap* TOP MARK DS1644+120 DS1644-120 DS1644P+120 DS1644P-120 *DS9034-PCX, DS9034I-PCX, DS9034-PCX+ required (must be ordered separately). A "+" indicates a lead-free product. The top mark will include a "+" symbol on lead-free devices. 1 of 13 REV: 040805 DS1644/DS1644P PIN DESCRIPTION PDIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN PowerCap 32 30 25 24 23 22 21 20 19 18 16 15 14 17 13 12 11 10 9 8 28 7 29 27 26 31 6 5 4 1-3,33,34 NAME A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND DQ3 DQ4 DQ5 DQ6 DQ7 CE A10 OE A11 A9 A8 A13 WE VCC RST NC X1, X2, VBAT FUNCTION Address Input Data Input/Output Ground Data Input/Output Active Low Chip-Enable Input Address Input Active Low Output-Enable Input Address Input Active-Low Write-Enable Input Power-Supply Input Active-Low Reset Output, Open Drain. Requires a pullup resistor for proper operation. No Connection Crystal Connection VBAT Battery Connection DESCRIPTION The DS1644 is a 32k x 8 nonvolatile static RAM with a full function real time clock, which are both accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to any JEDEC standard 32k x 8 SRAM. The device can also be easily substituted for ROM, EPROM and EEPROM, providing read/write nonvolatility and the addition of the real time clock function. The real time clock information resides in the eight uppermost RAM locations. The RTC registers contain year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1644 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-oftolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided. 2 of 13 DS1644/DS1644P PACKAGES The DS1644 is available in two packages (28-pin DIP and 34-pin PowerCap module). The 28-pin DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the DS1644P after the completion of the surface-mount process. Mounting the PowerCap after the surface mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap is DS9034PCX. CLOCK OPERATIONS--READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1644 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register. As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was present at the moment the halt command was issued. However, the internal clock registers of the double-buffered system continue to update so that the clock accuracy is not affected by the access of data. All of the DS1644 registers are updated simultaneously after the clock status is reset. Updating is within a second after the read bit is written to 0. DS1644 BLOCK DIAGRAM Figure 1 DS1644 TRUTH TABLE Table 1 VCC CE OE WE 5V 10% <4.5V >VBAT X X X VIL VIH X X X X VIL VIH VIH X X MODE DESELECT DESELECT WRITE READ READ DESELECT DESELECT DQ HIGH-Z HIGH-Z DATA IN DATA OUT HIGH-Z HIGH-Z HIGH-Z POWER STANDBY STANDBY ACTIVE ACTIVE ACTIVE CMOS STANDBY DATA RETENTION MODE 3 of 13 DS1644/DS1644P SETTING THE CLOCK The MSB Bit, (B7) of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts updates to the DS1644 registers. The user can then load them with the correct day, date and time data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters and allows normal operation to resume. STOPPING AND STARTING THE CLOCK OSCILLATOR The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB for the seconds registers. Setting it to a 1 stops the oscillator. FREQUENCY TEST BIT Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid (i.e., CE low, OE low, and address for seconds register remain valid and stable). CLOCK ACCURACY (DIP MODULE) The DS1644 is guaranteed to keep time accuracy to within 1 minute per month at 25C. The RTC is calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require additional calibration. For this reason, methods of field clock calibration are not available and not necessary. Clock accuracy is also affected by the electrical environment and caution should be taken to place the RTC in the lowest level EMI section of the PCB layout. For additional information please see application note 58. CLOCK ACCURACY (POWERCAP MODULE) The DS1644 and DS9034PCX are each individually tested for accuracy. Once mounted together, the module will typically keep time accuracy to within 1.53 minutes per month (35 ppm) at 25C. Clock accuracy is also affected by the electrical environment and caution should be taken to place the RTC in the lowest level EMI section of the PCB layout. For additional information please see application note 58. 4 of 13 DS1644/DS1644P DS1644 REGISTER MAP--BANK1 Table 2 ADDRESS 7FFF 7FFE 7FFD 7FFC 7FFB 7FFA 7FF9 7FF8 OSC = STOP BIT W = WRITE BIT B7 -- X X X X X OSC W B6 -- X X FT X -- -- R R = READ BIT X = UNUSED B5 -- X X -- -- -- X DATA B4 B3 -- -- -- -- -- -- X X -- -- -- -- -- -- X X FT = FREQUENCY TEST B2 -- -- -- -- -- -- -- X B1 -- -- -- -- -- -- -- X B0 -- -- -- -- -- -- -- X FUNCTION Year Month Date Day Hour Minutes Seconds Control 00-99 01-12 01-31 01-07 00-23 00-59 00-59 A Note: All indicated "X" bits are unused but must be set to "0" during write cycles to ensure proper clock operation. RETRIEVING DATA FROM RAM OR CLOCK The DS1644 is in the read mode whenever WE (write enable) is high, and CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address access. WRITING DATA TO RAM OR CLOCK The DS1644 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring high to low transition of WE or CE . The addresses must be held valid throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ after WE goes active. 5 of 13 DS1644/DS1644P DATA RETENTION MODE When VCC is within nominal limits (VCC > 4.5 volts) the DS1644 can be accessed as described above with read or write cycles. However, when VCC is below the power-fail point VPF (point at which write protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished internally by inhibiting access via the CE signal. At this time the power-fail output signal ( PFO ) will be driven active low and will remain active until VCC returns to nominal levels. When VCC falls below the level of the internal battery supply, power input is switched from the VCC pin to the internal battery and clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal level. 6 of 13 DS1644/DS1644P ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground.....................................................-0.3V to +7.0V Storage Temperature...............................................................-40C to +85C, Noncondensing Soldering Temperature......................................+260C for 10 seconds (DIP Package) (See Note 7) See IPC/JEDEC Standard J-STD-020A for Surface-Mount Devices This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. OPERATING RANGE RANGE Commercial TEMPERATURE 0C to +70C, Noncondensing VCC 5V 10% RECOMMENDED DC OPERATING CONDITIONS PARAMETER Supply Voltage Logic 1 Voltage All Inputs Logic 0 Voltage All Inputs SYMBOL VCC VIH VIL MIN 4.5 2.2 -0.3 (Over the Operating Range) TYP MAX 5.5 VCC+0.3 0.8 UNITS V V V NOTES 1 DC ELECTRICAL CHARACTERISTICS PARAMETER Average VCC Power Supply Current TTL Standby Current ( CE =VIH) CMOS Standby Current ( CE =VCC0.2V) Input Leakage Current (any input) Output Leakage Current Output Logic 1 Voltage (IOUT = -1.0 mA) Output Logic 0 Voltage (IOUT = +2.1 mA) Power-Fail Voltage SYMBOL ICC1 ICC2 ICC3 IIL IOL VOH VOL VPF 4.0 MIN (Over the Operating Range) TYP MAX 75 6 4.0 +1 +1 UNITS mA mA mA mA mA V V V NOTES 3 3 3 -1 -1 2.4 0.4 4.5 7 of 13 DS1644/DS1644P AC ELECTRICAL CHARACTERISTICS PARAMETER Read Cycle Time Address Access Time CE Access Time CE Data Off Time Output Enable Access Time Output Enable Data Off Time Output Enable to DQ Low-Z CE to DQ Low-Z Output Hold from Address Write Cycle Time Address Setup Time CE Pulse Width Address Hold from End of Write Write Pulse Width WE Data Off Time WE or CE Inactive Time Data Setup Time Data Hold Time High SYMBOL tRC tAA tCEA tCEZ tOEA tOEZ tOEL tCEL tOH tWC tAS tCEW tAH1 tAH2 tWEW tWEZ tWR tDS tDH1 tDH2 MIN 120 (Over the Operating Range) TYP MAX 120 120 40 100 40 5 5 5 120 0 100 5 30 75 40 10 85 0 15 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 5 6 5 6 AC TEST CONDITIONS Input Levels: Transition Times: 0V to 3V 5 ns CAPACITANCE PARAMETER Capacitance on all pins (except DQ) Capacitance on DQ pins SYMBOL CI CDQ MIN TYP MAX 7 10 (TA = +25C) UNITS pF pF NOTES AC ELECTRICAL CHARACTERISTICS (POWER-UP/DOWN TIMING) PARAMETER CE or WE at VIH before Power Down VPF (Max) to VPF (Min) VCC Fall Time VPF (Min) to VSO VCC Fall Time VSO to VPF (Min) VCC Rise Time VPF (Min) to VPF (Max) VCC Rise Time Power-Up Expected Data Retention Time (Oscillator On) SYMBOL tPD tF tFB tRB tR tREC tDR MIN 0 300 10 1 0 15 10 (Over the Operating Range) TYP MAX UNITS ms ms ms ms ms ms years NOTES 35 4 8 of 13 DS1644/DS1644P DS1644 READ CYCLE TIMING DS1644 WRITE CYCLE TIMING 9 of 13 DS1644/DS1644P POWER-DOWN/POWER-UP TIMING OUTPUT LOAD 10 of 13 DS1644/DS1644P NOTES: 1. All voltages are referenced to ground. 2. Typical values are at 25C and nominal supplies. 3. Outputs are open. 4. Data retention time is at 25C and is calculated from the date code on the device package. The date code XXYY is the year followed by the week of the year in which the device was manufactured. For example, 9225 would mean the 25th week of 1992. 5. tAH1, tDH1 are measured from WE going high. 6. tAH2, tDH2 are measured from CE going high. 7. Real-Time Clock Modules (DIP) can be successfully processed through conventional wave-soldering techniques as long as temperatures as long as temperature exposure to the lithium energy source contained within does not exceed +85C. Post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. In addition, for the PowerCap version: a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder reflow oriented with the label side up ("live - bug"). b. Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3 (three) seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder. 11 of 13 DS1644/DS1644P PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) DS1644 28-PIN PACKAGE PKG DIM A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM 28-PIN MIN 1.470 37.34 0.715 18.16 0.335 8.51 0.075 1.91 0.015 0.38 0.140 3.56 0.090 2.29 0.590 14.99 0.010 0.25 0.015 0.38 MAX 1.490 37.85 0.740 18.80 0.365 9.27 0.105 2.67 0.030 0.76 0.180 4.57 0.110 2.79 0.630 16.00 0.018 0.45 0.025 0.64 DS1644P PKG DIM A B C D E F G INCHES MIN 0.920 0.980 0.052 0.048 0.015 0.025 NOM 0.925 0.985 0.055 0.050 0.020 0.027 MAX 0.930 0.990 0.080 0.058 0.052 0.025 0.030 NOTE FOR THE PowerCap VERSION: a. DALLAS SEMICONDUCTOR RECOMMENDS THAT PowerCap MODULE BASES EXPERIENCE ONE PASS THROUGH SOLDER REFLOW ORIENTED WITH THE LABEL SIDE UP ("LIVE - BUG"). b. HAND SOLDERING AND TOUCH-UP: DO NOT TOUCH OR APPLY THE SOLDERING IRON TO LEADS FOR MORE THAN 3 SECONDS. TO SOLDER, APPLY FLUX TO THE PAD, HEAT THE LEAD FRAME PAD AND APPLY SOLDER. TO REMOVE THE PART, APPLY FLUX, HEAT THE LEAD FRAME PAD UNTIL THE SOLDER REFLOWS AND USE A SOLDER WICK TO REMOVE SOLDER. 12 of 13 DS1644/DS1644P DS1644P WITH DS9034PCX ATTACHED PKG DIM A B C D E F G INCHES MIN 0.920 0.955 0.240 0.052 0.048 0.015 0.020 NOM 0.925 0.960 0.245 0.055 0.050 0.020 0.025 MAX 0.930 0.965 0.250 0.058 0.052 0.025 0.030 RECOMMENDED POWERCAP MODULE LAND PATTERN PKG DIM A B C D E INCHES MIN - NOM 1.050 0.826 0.050 0.030 0.112 MAX - 13 of 13 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products * Printed USA The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. |
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